This invention relates to programmable logic integrated circuit devices, and more particularly to configurable phase-locked loop (PLL) circuitry for programmable logic devices.
Programmable logic integrated circuit devices are well known and often include large numbers of programmable logic blocks, memory blocks, and programmable interconnection resources. Logic blocks are programmable by a user to perform various logic functions desired by the user. Memory blocks may be used by the user to store and subsequently output data. Interconnection resources are programmable by the user to make any of a wide range of connections between inputs of the programmable logic device and inputs of the logic and memory blocks, between outputs of the logic and memory blocks and outputs of the device, and between outputs and inputs of the logic and memory blocks. Although each logic block is typically able to perform only a relatively small logic task, such interconnections allow the programmable logic device to perform extremely complex logic functions.
Providing PLL circuitry on programmable logic devices is also well known. PLL circuitry produces an output signal that is continually adjusted to maintain a constant frequency and phase relationship with an input reference signal (the PLL circuitry thus “locks” onto that frequency and phase relationship). PLL circuitry may be used to counteract clock signal propagation delay on the programmable logic device, convert from one clock signal frequency (e.g., an input clock signal frequency) to another different clock signal frequency (e.g., to be output by the device), and more generally to provide one or more external clock signals, internal global clock signals, or internal local/regional clock signals.
The configurability of known PLL circuitry, however, is typically limited. For example, the frequency range of output signals produced by known PLL circuitry may be too narrow for many applications in which a programmable logic device could be used. Furthermore, the number and configurability of PLL outputs may be too limited. For example, known PLL circuitry may not have enough outputs available for connection to I/O pins for off-chip clocking applications. Moreover, known PLL circuitry may not have enough outputs available for connection to on-chip global or local clocking networks. Thus, the configurability of known PLL circuitry on programmable logic devices may limit the number of designs that can be implemented on the device and thus the number of applications in which a programmable logic device could otherwise be used.
In view of the foregoing, it would be desirable to be able to provide highly configurable PLL circuitry in order to increase the number of designs and applications in which programmable logic devices can be used.